| 发明名称 |
DATA PROCESSING SYSTEM HAVING COMBINED MEMORY BLOCK AND STACK PACKAGE |
| 摘要 |
A data processing system includes a central processing unit (CPU), a control block configured to interface with the CPU, a cache memory configured to interface with the control block and arranged to be spaced from the CPU by a first distance, and a combined memory block configured to interface with the control block, arranged to be spaced from the CPU by a second distance larger than the first distance, and configured of a working memory and a storage memory. The combined memory block is configured of a plurality of stacked memory layers, each configured of a plurality of variable resistance memory cells. The working memory is allocated to one memory layer selected among the plurality of memory layers. The storage memory is allocated to remaining memory layers among the plurality of memory layers. |
| 申请公布号 |
US2016210235(A1) |
申请公布日期 |
2016.07.21 |
| 申请号 |
US201615063012 |
申请日期 |
2016.03.07 |
| 申请人 |
SK hynix Inc. |
发明人 |
PARK Hae Chan;KIM Sung Cheoul;KIM Tae Ho |
| 分类号 |
G06F12/08;G06F13/40 |
主分类号 |
G06F12/08 |
| 代理机构 |
|
代理人 |
|
| 主权项 |
1. A data processing system comprising:
a central processing unit (CPU); a control block configured to interface with the CPU; a cache memory configured to interface with the control block and arranged to be spaced from the CPU by a first distance; and a combined memory configured to interface with the control block, arranged to be spaced from the CPU by a second distance larger than the first distance, and comprising a working memory and a storage memory, wherein the combined memory comprises a plurality of stacked memory layers, each memory layer comprising a plurality of variable resistance memory cells, the working memory is allocated to one memory layer selected from among the plurality of memory layers, and the storage memory is allocated to remaining memory layers among the plurality of memory layers. |
| 地址 |
Gyeonggi-do KR |
