发明名称 Secure fast packet switch having improved memory utilization
摘要 In a secure fast packet switch having a plurality of input ports and a plurality of output ports, a method of determining which port in the plurality of output ports data that is received on one input port in the plurality of input ports is to be sent to, the method including the steps of determining a physical layer address of a sending node, determining a physical layer address of a receiving node, determining an input port in the plurality of input ports that the data was received on, determining if the physical layer address of the sending node and the physical layer address of the receiving node are an allowed combination, determining the magnitude of the node identification number of the sending node, determining the magnitude of the node identification number of the receiving node, obtaining outbound port information from a first predetermined location in a data structure stored in a memory if the node identification number of the sending node is greater than the node identification number of the receiving node, and obtaining outbound port information from a second predetermined location in the data structure stored in the memory if the node identification number of the sending node is less than the node identification number of the receiving node. Circuitry that carries out the method is also described along with an exemplary data structure.
申请公布号 US2003048779(A1) 申请公布日期 2003.03.13
申请号 US20000578143 申请日期 2000.05.24
申请人 DOHERTY JAMES P.;GRIMES ANDREW 发明人 DOHERTY JAMES P.;GRIMES ANDREW
分类号 H04L12/24;H04L12/26;H04L12/56;H04L29/06;(IPC1-7):H04L12/56 主分类号 H04L12/24
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