| 发明名称 |
CONTROLLER, SEMICONDUCTOR MEMORY SYSTEM AND OPERATING METHOD THEREOF |
| 摘要 |
An operating method of a controller that includes: when a first ECC decoding on data read from a semiconductor memory device according to a hard read voltage fails, generating one or more quantization intervals based on the number of unsatisfied syndrome check (USC), which is a result of the first ECC decoding; and performing a second ECC decoding on the data by generating soft read data according to soft read voltages determined by the hard read voltage and the quantization intervals. |
| 申请公布号 |
US2016246673(A1) |
申请公布日期 |
2016.08.25 |
| 申请号 |
US201514743914 |
申请日期 |
2015.06.18 |
| 申请人 |
SK hynix Inc. |
发明人 |
KIM Jae-Bum |
| 分类号 |
G06F11/10;G11C16/26;H03M13/15;G11C29/52;H03M13/11 |
主分类号 |
G06F11/10 |
| 代理机构 |
|
代理人 |
|
| 主权项 |
1. An operating method of a controller, comprising:
when a first ECC decoding on data read from a semiconductor memory device according to a hard read voltage fails, generating one or more quantization intervals based on a number of unsatisfied syndrome check (USC), which is a result of the first ECC decoding; and performing a second ECC decoding on the data by generating soft read data according to soft read voltages determined by the hard read voltage and the quantization intervals. |
| 地址 |
Gyeonggi-do KR |
