摘要 |
<p>In a processor arrangement comprising a Z 80 processor (1), intended for terminal functions, information relating to the characters is sent to a type I 8275 cathode ray tube in a cycle necessary for image regeneration, from a dynamic memory (2) and passing via an external data bus (103). The image regeneration process is effected in the memory regeneration cycles by means of an address multiplexer (21), which connects the external address bus (102) of the memory (2), during simultaneous memory and image regeneration cycles, to the output of a display address counter (22) containing the address of the start of the memory. Two flip-flops (20, 19) ensure the writing of the data of the characters extracted, the shifting of the above-mentioned counter (22) and the control of the address multiplexer (21). The tripping of said flip-flops is permitted during the image regeneration processor cycles during data request; during regeneration, addressing of the memory (2) by a unit (18) which delays the cycle control operated by the processor (1) is permitted. The invention also concerns the representation of ''capital-letter'' characters from signals supplied by the cathode ray tube monitor (4). For this purpose, a multiplexer (36, 37) is connected respectively between the cathode ray tube control (4) and a character generator (30), also between a pulse generator (39) and a frequency divider (38) connected thereto, as well as an incremential register (31) controlled by the character generator (30). The insertion and synchronization of said multiplexer enable the use of ''capital-letter'' displays, and any desired attribute characters.</p> |