| 摘要 |
A Schottky diode (12) whose fabrication is adapted to a CMOS process is disclosed. The Schottky diode (12) is formed in an N- well (24). A spacer (40) is formed over the N- well (24), then an N+ region (52) is implanted along one side of the spacer (40). The spacer (40) is structurally similar to a CMOS transistor (14, 16) gate structure (38), and the N+ implantation process is the same one which is used to implant N+ source and drain regions (53) in an NMOS transistor (16). A guard ring (60) is implanted using the same process steps which are used to implant source and drain regions (56) for a PMOS transistor (14). A silicide (62) contacts the N- well region (24) along an opposing side of the spacer (40) to form a rectifying junction. This silicide (62) is additionally used in the CMOS transistors (14, 16) to lower contact resistance in conductive semiconductor regions (38, 53, and 56).
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