| 摘要 |
<p>PURPOSE:To improve the using efficiency of a buffer memory constituting a bus matrix, to lower the cost of a device and to improve reliability by separating an input packet to a data part and a control part and separately executing the exchange processing of the data part and the exchange processing of the control part. CONSTITUTION:The packets sent from transmission buffer circuits 40.1-40.n are separated to data packets and control packets in input traffic transfer control circuits 20.1-20.n and the data packets are transferred to a bus matrix part 10 with transfer control circuits 21.1-21.n. The control packets are sent to a line 5 for control packet transfer by control packet transmission control circuits 22.1-22.n. Control packet reception control circuits 32.1-32.n extract the control packets, for which the circuits themselves are destinations, from the line 5 and output traffic transfer control circuits 30.1-30.n extract the data packets, for which the circuits themselves are destinations, from the bus matrix part 10. Then, the control packets from the control circuits 32.1-32.n are added to these data packets and sent to output packet transfer buses 2.1-2.n.</p> |
