| 摘要 |
PURPOSE: To provide a clock reproducing circuit which reduces the clock jitters and can perform a fast operation. CONSTITUTION: When an NRZ signal is inputted to a sampling pulse generation circuit 1, the circuit 1 outputs the sampling pulses SSP of the prescribed width W at every rise and fall of the NRZ signal. A sample-and-hold circuit 2 is actuated by the pulse SSP and samples the clock signal CLK received from a voltage control oscillator 4. As a result, the circuit 2 outputs a sample-and- hold signal SSH of the voltage accordant with the phase of the signal CLK acquired when the pulse SSP is produced. The sample-and-hold voltage value is kept until the next pulse SSP is produced. |
