| 摘要 |
PROBLEM TO BE SOLVED: To hold data on peripheral equipment in a device cache regardless of the access frequency/capacity of peripheral equipment. SOLUTION: Device ID signals 21, 22 and 23 which value peripheral equipment 11, 12 and 13 have and the value of a cache size register 6 defining the sizes of respective device cache areas are inputted to a cache address arithmetic circuit 5 that a memory controller 2 has and addresses are operated. The addresses are outputted to a main storage device 3 and data which is read from peripheral equipment 11 is written into a device cache area 31 designated by the address. Data which is read from peripheral equipment 12 is written into a device cache area 32 and data which is read from peripheral equipment 13 is written into a device cache area 33.
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