| 摘要 |
An arrangement ( 100 ) and method for sigma-delta analog-to-digital conversion by providing parallel translating sigma-delta analog-to-digital converters ( 21, 22 ) and summing their outputs to produce a digital output signal having a bandwidth greater than that of the first or second translating sigma-delta analog-to-digital converters ( 21, 22 ). The parallel translating sigma-delta analog-to-digital converters ( 21, 22 ) use switching sequences arranged to cancel third and fifth harmonics in the digital output signal. Orthogonality error in the switching sequences applied to the sigma-delta modulators is compensated by adjusting the phase of the signals applied to mixers ( 51, 52 ).
|
