Circuits and methods of TAF-DPS vernier caliper for time-of-flight measurement

摘要

Circuits for measuring TOF between two electrical signals comprises 1) a slow TAF-DPS clock signal generator for generating a slow clock signal, a fast TAF-DPS clock signal generator for generating a fast clock signal, said slow TAF-DPS clock signal generator comprises a gated ring oscillator and a TAF-DPS frequency synthesizer, said fast TAF-DPS clock signal generator comprises a gated ring oscillator and a TAF-DPS frequency synthesizer; 2) a phase detector for receiving said slow and fast clock signals and detecting point-of-coincidence between said slow and fast clock signals; 3) a first digital counter driven by said slow clock signal for storing the number of slow clock cycles and a second digital counter driven by said fast clock signal for storing the number of fast clock cycles; 4) a calibrator for calibrating said gate ring oscillators; 5) a calculation block for calculating TOF measurement result. Methods of using a slow TAF-DPS clock generator and a fast TAF-DPS clock generator for measuring TOF between two electrical signals are also disclosed.

主权项

1. A system of measuring Time-of-Flight (TOF) between signal transitions of two electrical signals by using two clock generators, comprising:
a first input for receiving a first electrical signal; a second input for receiving a second electrical signal; a third input for receiving a frequency control word Fslow; a fourth input for receiving a frequency control word Ffast; a fifth input for receiving an electrical signal of known frequency; a sixth input for receiving an enable signal; an output for delivering TOF measurement result; a slow TAF-DPS (Time-Average-Frequency Direct Period Synthesis) clock generator for generating a slow clock signal, having a first input for receiving said first electrical signal, having a second input for receiving said frequency control word Fslow, having a first output for delivering said slow clock signal, having a second output for delivering an electrical signal for calibration; a fast TAF-DPS clock generator for generating a fast clock signal, having a first input for receiving said second electrical signal, having a second input for receiving said frequency control word Ffast, having a first output for delivering said fast clock signal, having a second output for delivering an electrical signal for calibration; a phase detector for detecting point-of-coincidence, having a first input for receiving said slow clock signal, having a second input for receiving said fast clock signal, having an output for delivering a reset signal; a first digital counter, having a clock input for receiving said slow clock signal, having a reset input for receiving said reset signal from said phase detector; having an output for outputting its content; a second digital counter, having a clock input for receiving said fast clock signal, having a reset input for receiving said reset signal from said phase detector; having an output for outputting its content; a calibration block, having an enable input for receiving a signal from said sixth input, having a calibration input for receiving a signal from said fifth input, having a first oscillation input for receiving signal from said second output of slow TAF-DPS clock generator, having a second oscillation input for receiving signal from said second output of fast TAF-DPS clock generator, having an output for delivering calibration result; a calculation block, having a first input for receiving a first digital value, having a second input for receiving a second digital value, having a third input for receiving a third digital value, having an output for delivering calculation result; wherein said output of said calculation block is connected to said output; wherein said output of first digital counter is connected to said first input of said calculation block; wherein said output of second digital counter is connected to said second input of said calculation block; wherein said output of calibration block is connected to said third input of said calculation block.