| 摘要 |
The present invention is to suppress the decline of a potential of a gate of a pull-up transistor. The first transistor having a driving circuit is configured such that a first terminal is electrically connected to a second wiring, the second terminal is electrically connected to a first wiring, a gate is electrically connected to the first terminal of the second circuit and the third transistor. The second transistor is configured such that a first terminal is electrically connected to a first wiring, a second terminal is electrically connected to a sixth writing, a gate is electrically connected to the gate of the first circuit and the third transistor. The third transistor is configured such that a second terminal is electrically connected to a sixth wiring, a first circuit is electrically connected to a third wiring, a fourth wiring, a fifth wiring and a sixth wiring, and a second circuit is electrically connected to a first wiring, a second wiring and a sixth wiring. |
