发明名称 Methods, apparatus, and systems for secure demand paging and other paging operations for processor devices
摘要 A secure demand paging system (1020) includes a processor (1030) operable for executing instructions, an internal memory (1034) for a first page in a first virtual machine context, an external memory (1024) for a second page in a second virtual machine context, and a security circuit (1038) coupled to the processor (1030) and to the internal memory (1034) for maintaining the first page secure in the internal memory (1034). The processor (1030) is operable to execute sets of instructions representing: a central controller (4210), an abort handler (4260) coupled to supply to the central controller (4210) at least one signal representing a page fault by an instruction in the processor (1030), a scavenger (4220) responsive to the central controller (4210) and operable to identify the first page as a page to free, a virtual machine context switcher (4230) responsive to the central controller (4210) to change from the first virtual machine context to the second virtual machine context; and a swapper manager (4240) operable to swap in the second page from the external memory (1024) with decryption and integrity check, to the internal memory (1034) in place of the first page.
申请公布号 US9438424(B2) 申请公布日期 2016.09.06
申请号 US201414458592 申请日期 2014.08.13
申请人 TEXAS INSTRUMENTS INCORPORATED 发明人 Goss Steven;Conti Gregory Remy Philippe;Shankar Narendar M.;Akkar Mehdi-Laurent;Vial Aymeric
分类号 H04L9/32;G06F12/14;G06F21/57;H04L29/06;G06F12/08;G06F21/79;H04W12/06 主分类号 H04L9/32
代理机构 代理人 Neerings Ronald O.;Cimino Frank D.
主权项 1. A secure demand paging (SPD) system comprising: an external volatile memory; a microprocessor coupled to said external volatile memory, said microprocessor having a secure internal memory having a physical address space, and said microprocessor is operable to: execute at least one protected application in the secure internal memory;execute a client application at intervals and also have at least one interval of lower-activity status;selectively perform the page scavenging so that page wiping is included and a swap out of a modified wiped page is deferred; andestablish a queue identifying pages for which swap out is deferred; and a non-volatile memory storing a coded physical representation of operations accessible by said microprocessor including a representation of an SDP protected application including a page scavenger, and an operation to schedule the page scavenger for said at least one interval of lower-activity status.
地址 Dallas TX US