发明名称 Microprocessor with multiple low power modes and emulation apparatus for said microprocessor
摘要 A microprocessor comprises a central processing unit receiving a first clock signal, a plurality of peripherals receiving a second clock signal a first select unit for selecting the first clock signal out of a plurality of clock signals and a second select unit for selecting the second clock signal out of the plurality of clock signals. The central processing unit comprises an execution unit which controls the select units upon execution of a low power mode instruction to select a clock signal for the central processing unit and the peripheral units.
申请公布号 US2003079152(A1) 申请公布日期 2003.04.24
申请号 US20010929622 申请日期 2001.08.14
申请人 TRIECE JOSEPH W. 发明人 TRIECE JOSEPH W.
分类号 G06F1/32;(IPC1-7):G06F1/26;G06F1/28;G06F1/30 主分类号 G06F1/32
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