发明名称 CLOCK SKEW SUPPRESSING CIRCUIT
摘要 PURPOSE:To suppress clock skew without enlarging the buffer size by applying a clock signal to one input of a differential amplifier, applying a constant voltage to the other input and applying a signal extracted from the inverted output or non-inverted output of the differential amplifier to an internal circuit. CONSTITUTION:A clock signal CLKLOCAL to be transmitted through a transmission line provided with a buffer or wiring to the internal circuit of a semiconductor chip is applied to one input (+) of a differential amplifier 20. A constant potential VREF is applied to another input (-). Corresponding to this potential, the transition time of a non-inverted output CLKOUT of the differential amplifier 20 is changed. While the potential on the reference side (-) is set at a low level, for example, when the potential on the comparison side (+) is enlarged a little, the output state is immediately transited but while the potential on the reference side (-) is set at a high level, the output state is not transited until the potential on the comparison side (+) is increased to a high level. Therefore, the skew can be suppressed by adjusting the transition time of the output.
申请公布号 JPH07131308(A) 申请公布日期 1995.05.19
申请号 JP19930271371 申请日期 1993.10.29
申请人 FUJITSU LTD 发明人 HIGAKI NAOSHI
分类号 G06F1/10;H03K5/00;H03K5/13;H03L7/00 主分类号 G06F1/10
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