CIRCUIT AND METHOD FOR CLOCK CONTROL

摘要

PROBLEM TO BE SOLVED: To provide a circuit and a method for clock control which can decrease a circuit scale and eliminate a delay difference in a short time as compared with the case wherein a PLL circuit and a DLL circuit are used as a circuit which eliminates a delay difference on the whole clock transmission line. SOLUTION: This circuit is equipped with a timing averaging circuit (10) which inputs clocks from a certain position on the going path 111 of a clock propagation path where an input clock is inputted from one end and returned and a position on the return path 112 corresponding to the above position and averages the timing difference between those clocks and outputs.