发明名称 |
Memory architecture for increased speed and reduced power consumption |
摘要 |
An improved multi-wordline memory architecture providing decreased bitline coupling to increase speed and reduce power consumption including an interleaving arrangement for connecting adjacent bitcells to different wordlines, coupled to a multiplexing arrangement for sharing bitlines of adjacent bitcells.
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申请公布号 |
US7035132(B2) |
申请公布日期 |
2006.04.25 |
申请号 |
US20030426004 |
申请日期 |
2003.04.29 |
申请人 |
STMICROELECTRONICS PVT. LTD |
发明人 |
NAUTIYAL VIVEK;KUMAR ASHISH |
分类号 |
G11C11/00;G11C7/18;G11C8/14 |
主分类号 |
G11C11/00 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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