发明名称 REFERRENCE VOLTAGE GENERATION CIRCUIT
摘要 PROBLEM TO BE SOLVED: To provide a reference voltage generation circuit capable of preventing the oscillation of output voltage and reducing power consumption. SOLUTION: This reference voltage generation circuit is constituted of comparators 1, 2, 5, a PMOS transistor(TR) 3, NMOS TR 4, and a bias current adjusting circuit 6 for receiving a comparison output from the comparator 5 and controlling the bias currents of the comparators 1, 2. Voltage inputs V1 , V2 from input terminals 7, 8 are respectively inputted to the positive phase input terminals of the comparators 1, 2 and output voltage V0 is fed back and inputted to the reverse phase input terminals of the comparators 1, 2. Voltage outputs from the comparators 1, 2 are respectively inputted to the gates of the TRs 4, 3, voltage V3 from an input terminal 9 is inputted to the positive phase input terminal of the comparator 5, the output voltage V0 is inputted to the reverse phase input therminal of the comparator 5, and the circuit 6 executes current control action based upon the comparison output from the comparator 5.
申请公布号 JPH09212247(A) 申请公布日期 1997.08.15
申请号 JP19960014060 申请日期 1996.01.30
申请人 NEC CORP 发明人 OGAWARA TAKESHI
分类号 H02J1/00;G05F1/618;G05F3/24 主分类号 H02J1/00
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