DATA TRANSFER METHOD FOR INTEGRATED CIRCUIT AND ITS DEVICE

摘要

PROBLEM TO BE SOLVED: To attain data transfer at a high speed without using a PLL circuit making the state of the device unstable for a lock time and requiring much chip area. SOLUTION: A data output device 100 reads data to be transferred by a D-FF 101 synchronously with an external clock signal CLK fed to a clock signal input terminal 104 and sends the data to a data output line via an output buffer 102 and an output terminal 105 and uses an output buffer 106 to delay the external clock signal CLK and outputs the delayed clock signal CLKd to a clock output line. Transfer data D1 are received by a data input device 200 via a data input terminal 205 and allows a D-FF 201 to latch the data synchronously with the delayed clock signal received via a clock signal input terminal 204. The transfer data in the D-FF 201 are read by a next stage D-FF 202 synchronously with the external clock signal at the clock input terminal 203 as received data Di.