Local word line decoder for memory with 2 MOS devices

摘要

A method and a circuit are disclosed by which the semiconductor area is reduced that a local word line decoder for a memory array requires. This reduction in area size has been achieved by eliminating one transistor of a three transistor local wordline decoder and by reducing the number of inputs to the decoder from three to two. The reduction in inputs is made possible by the method of applying to one of the inputs, when low, a voltage signal vb which is at least one threshold lower than the voltage signal to the other input, when low. This voltage vb can be derived from the p-substrate bias voltage.