发明名称 |
Methods for manufacturing semiconductor devices having chamfered metal silicide layers |
摘要 |
Methods for manufacturing a semiconductor device, in which a chamfered metal silicide layer is formed by a 2-stage continuous wet etching process using different etchants, thereby resulting in a sufficient insulation margin between a lower conductive layer including the metal silicide layer and the contact plug self-aligned with the lower conductive layer are disclosed. In the manufacture of a semiconductor device, a mask pattern is formed on a metal silicide layer to expose a portion of the metal silicide layer. The exposed portion of the metal silicide layer is isotropically etched in a first etchant to form a metal silicide layer with a shallow groove, and defects due to the silicon remaining on the surface of the metal silicide layer with the shallow groove are removed using a second etchant, to form a metal silicide layer with a smooth surface. Microelectronic structures produced by methods of the present invention are also disclosed.
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申请公布号 |
US6331478(B1) |
申请公布日期 |
2001.12.18 |
申请号 |
US20000685456 |
申请日期 |
2000.10.09 |
申请人 |
SAMSUNG ELECTRONICS CO., LTD. |
发明人 |
LEE KEUM-JOO;HWANG IN-SEAK;KO YONG-SUN;SONG CHANG-IYOUNG |
分类号 |
H01L21/24;H01L21/28;H01L21/306;H01L21/3205;H01L21/3213;H01L21/336;H01L21/4763;H01L21/60;H01L21/768;H01L21/8242;H01L23/52;H01L29/423;H01L29/43;H01L29/49;H01L29/78;(IPC1-7):H01L21/476 |
主分类号 |
H01L21/24 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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