发明名称 Apparatus and method for forming a battery in an intergrated circuit
摘要 A method and structure that provides a battery within an integrated circuit for providing voltage to low-current electronic devices that exist within the integrated circuit. The method includes Front-End-Of-Line (FEOL) processing for generating a layer of electronic devices on a semiconductor wafer, followed by Back-End-Of-Line (BEOL) integration for wires the electronic devices together to form completed electrical circuits of the integrated circuit. The BEOL integration includes forming a multilayered structure of wiring levels on the layer of electronic devices. Each wiring level includes conductive metallization (e.g., metal-plated vias, conductive wiring lines, etc.) embedded in insulative material. The battery is formed during BEOL integration within one or more wiring levels, and the conductive metallization conductively couples positive and negative terminals of the battery to the electronic devices. The battery may have several different topologies relative to the structural and geometrical relationships among the battery electrodes and electrolyte. Multiple batteries may be formed within one or more wiring levels, and may be conductively coupled to the electronic devices. The multiple batteries may be connected in series or in parallel.
申请公布号 US2002093029(A1) 申请公布日期 2002.07.18
申请号 US20010761123 申请日期 2001.01.16
申请人 BALLANTINE ARNE W.;GROVES ROBERT A.;LUND JENNIFER L.;NAKOS JAMES S.;RICE MICHAEL B.;STAMPER ANTHONY K. 发明人 BALLANTINE ARNE W.;GROVES ROBERT A.;LUND JENNIFER L.;NAKOS JAMES S.;RICE MICHAEL B.;STAMPER ANTHONY K.
分类号 H01L21/768;H01L21/822;H01L23/522;H01L23/58;H01L27/04;H01M4/58;H01M6/02;H01M6/18;H01M6/42;H01M10/052;H01M10/0562;H01M10/058;H01M10/36;H01M10/42;(IPC1-7):H01L29/04;H01L31/111;H01L31/20;H01L31/036;H01L23/52;H01L23/48;H01L31/037;H01L29/74;H01L23/053;H01L21/00 主分类号 H01L21/768
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