发明名称 |
Low power vector summation apparatus |
摘要 |
An low power vector summation apparatus is provided for using 2's complement arithmetic without the high switching activity of the prior art. In particular, the invention operates to exploit the sign-extension property of a 2's complement number. A reduced representation for 2's complement numbers is provided to avoid sign-extension and the switching of sign-extension bits. The maximum magnitude of a 2's complement number is detected and its reduced representation is dynamically generated to represent the signal. A constant error introduced by the reduced representation is also dynamically compensated.
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申请公布号 |
US7328227(B2) |
申请公布日期 |
2008.02.05 |
申请号 |
US20060359201 |
申请日期 |
2006.02.22 |
申请人 |
AGERE SYSTEMS INC. |
发明人 |
AZADET KAMERAN;YU MENG-LIN;YU ZHAN |
分类号 |
G06F7/00;G06F7/544;H03H17/02;H03H17/06 |
主分类号 |
G06F7/00 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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