Adaptive error correction codes (ECCs) for electronic memories

摘要

Systems and methods for adaptive error correction codes (ECCs) for electronic memories. In some embodiments, a memory device, may include a first memory having a plurality of address locations, each of the plurality of address locations having a number of storage bits configured to store data and one or more error correction bits corresponding to the data; and a second memory distinct from the first memory, the second memory having a plurality of entries, each of the plurality of entries configured to store one or more operation code bits relating to data stored at a corresponding address location in the first memory, the one or more operation code bits identifying an error correction scheme used to generate the one or more error correction bits at the corresponding address location in the first memory.

主权项

1. A memory device, comprising:
a first memory having a plurality of address locations, each of the plurality of address locations having a number of storage bits configured to store data and one or more error correction bits corresponding to the data; a second memory distinct from the first memory, the second memory having a plurality of entries, each of the plurality of entries configured to store one or more operation code bits relating to data stored at a corresponding address location in the first memory, the one or more operation code bits identifying an error correction scheme used to generate the one or more error correction bits at the corresponding address location in the first memory; and a logic circuit coupled to the first and second memory circuits, the logic circuit configured to:
determine that data stored at a given address location of the first memory includes a number of data corruption errors that exceeds a correction capability of a first correction scheme identified by a first operation code stored in a corresponding entry of the second memory;in response to the determination, select a second correction scheme capable of correcting the number of data corruption errors;update the corresponding entry of the second memory with a second operation code identifying the second correction scheme; andselect the second correction scheme for another address location independently of whether the first correction scheme is capable of correcting data corruption errors in the other address location.