发明名称 Integrated circuit decoupling capacitors
摘要 Power supply decoupling capacitors are provided for integrated circuits. The decoupling capacitors may be distributed in clusters amongst powered circuit components. Each cluster may contain a number of individual capacitor cells that are connected in parallel. Each capacitor cell may contain a capacitor and a resistor connected in series with the capacitor. The capacitors may be metal-insulator-metal (MIM) capacitors. The resistor in each cell may limit the current through an individual capacitor in the event of a short in the capacitor due to a dielectric defect.
申请公布号 US9425192(B2) 申请公布日期 2016.08.23
申请号 US200812332928 申请日期 2008.12.11
申请人 Altera Corporation 发明人 Rahim Irfan;Vest William Bradley;Wong Myron Wai
分类号 H01L29/00;H01L27/08;H01L23/522;H01L23/528 主分类号 H01L29/00
代理机构 代理人
主权项 1. An integrated circuit comprising: a power supply voltage path on which an adjustable power supply voltage is provided; a ground power supply path; a plurality of power supply decoupling capacitors distributed in a plurality of parallel clusters on the integrated circuit, wherein the plurality of parallel clusters of capacitor cells are coupled between the power supply voltage path and the ground power supply path; a first power source that is coupled to a power supply voltage path and the ground power supply path and that outputs a first voltage; a second power source that is coupled to the power supply voltage path and the ground power supply path and that outputs a second voltage that is lower than the first voltage; a first region of memory cells; a first multiplexer that receives the first and second voltages and that selectively outputs the first voltage to the first region of memory cells in response to determining that the first region of memory cells is to be placed in a fast mode; a second region of memory cells; and a second multiplexer that receives the first and second voltages and that selectively outputs the second voltage to the second region of memory cells in response to determining that the second region of memory cells is to be placed in a slow mode.
地址 San Jose CA US