| 摘要 |
<p>A variable delay circuit consists of a single-stage CMOS delay circuit (100) having an associated time delay between its input and output. A first transistor (M1) connects a voltage supply node to other portions of the single-stage CMOS delay circuit. The impedance of the first transistor (M1) corresponds to an associated time delay. A second transistor (M2), gated by a control signal, connects the voltage supply node and the other portions of the single-stage CMOS delay circuit in parallel with the first P-channel transistor (M1). The delay circuit delays signals for a longer period of time when the second transistor (M2) is disabled by said control signal than when the second transistor is enabled. In a variation on this delay circuit, a plurality of delay control elements (M2, M6, M7, M8) are coupled to the single-stage delay circuit, each accepting a distinct control signal and decreasing the delay circuits associated time delay to a corresponding shorter delay time when its control signal is enabled.</p> |
