Semiconductor memory device with clamping circuit for preventing malfunction

摘要

A semiconductor memory device includes: subarrays (1) having memory cells (511-514, 521-524) each arranged at cross points of a plurality of bit lines (Bn, Bn (n = 1-4)) and a plurality of word lines (WL0-WL255); a row decoder (2) for selecting among the word lines (WL0-WL255); a column decoder (3) for supplying a select signal to transfer gates (61-64, 71-74) for selecting among paired bit lines (Bn, Bn (n = 1-4, 10, 20, 30, 40)); and a clamping circuit (8) for fixing the potential of a column select line at a constant potential before the column decoder is activated. <IMAGE>