Decryption circuit for integrated circuit, has signals delivering unit to deliver decrypted signals on data lines, and initial clock signal inserting unit to insert respective initial state on lines between respective states of signals

摘要

The circuit has a signal producing unit (104) decrypting synchronized data encrypted signal (ds) and producing a data decrypted signal (de) and a complementary data decrypted signal (dqe). A signals delivering unit (106) permits to deliver the signals on data lines (B, BQ). An initial clock signal inserting unit (108) inserts respective initial states on the lines (B, BQ) between respective states of the data decrypted signals. Independent claims are also included for the following: (A) a logical cell including a decryption circuit and an encryption circuit (B) a method of executing a logical operation with double rail in a logical environment with unique rail.