发明名称 Fast evaluation of average critical area for IC layouts
摘要 Method and apparatus for approximating the average critical area of a layout or layout region, involving summing, over all the object segments of interest, respective critical area contribution values that are dependent upon particular layout parameters of the objects, each of the contribution values being representative of a plurality of defect sizes, and being defined such that for each defect size in the plurality of defect sizes, and for a particular defect type, the contribution values collectively count all critical areas arising due to the object segments of interest only once.
申请公布号 US7346865(B2) 申请公布日期 2008.03.18
申请号 US20040978946 申请日期 2004.11.01
申请人 SYNOPSYS, INC. 发明人 SU QING;SINHA SUBARNAREKHA;CHIANG CHARLES C.
分类号 G06F17/50 主分类号 G06F17/50
代理机构 代理人
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