发明名称 |
PHYSICALLY UNCLONABLE CAMOUFLAGE STRUCTURE AND METHODS FOR FABRICATING SAME |
摘要 |
An application specific integrated circuit (ASIC) and a method for its design and fabrication is disclosed. In one embodiment, the camouflaged application specific integrated circuit (ASIC), comprises a plurality of interconnected functional logic cells that together perform one or more ASIC logical functions, wherein the functional logic cells comprise a camouflage cell including: a source region of a first conductivity type, a drain region of the first conductivity type, and a camouflage region of a second conductivity type disposed between the source region and the drain region. The camouflage region renders the camouflage cell always off in a first camouflage cell configuration and always on in a second camouflage cell configuration having a planar layout substantially indistinguishable from the first configuration. |
申请公布号 |
US2016197616(A1) |
申请公布日期 |
2016.07.07 |
申请号 |
US201514985270 |
申请日期 |
2015.12.30 |
申请人 |
SypherMedia International, Inc. |
发明人 |
Cocchi Ronald P.;Chow Lap Wai;Baukus James P.;Wang Bryan J. |
分类号 |
H03K19/177;G06F17/50 |
主分类号 |
H03K19/177 |
代理机构 |
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代理人 |
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主权项 |
1. A camouflaged application specific integrated circuit (ASIC), comprising:
a plurality of interconnected functional logic cells that together perform one or more ASIC logical functions; wherein the functional logic cells comprise a camouflage cell including:
a source region of a first conductivity type;a drain region of the first conductivity type;a camouflage region of a second conductivity type disposed between the source region and the drain region; wherein the camouflage region renders the camouflage cell always off in a first camouflage cell configuration and always on in a second camouflage cell configuration having a planar layout substantially indistinguishable from the first configuration. |
地址 |
Westminster CA US |