发明名称 |
Execution of additional instructions in conjunction atomically as specified in instruction field |
摘要 |
A processor includes a plurality of execution units. At least one of the execution units is configured to determine, based on a field of a first instruction, a number of additional instructions to execute in conjunction with the first instruction and prior to execution of the first instruction. |
申请公布号 |
US9471317(B2) |
申请公布日期 |
2016.10.18 |
申请号 |
US201213628376 |
申请日期 |
2012.09.27 |
申请人 |
TEXAS INSTRUMENTS DEUTSCHLAND GMBH |
发明人 |
Diewald Horst;Zipperer Johann |
分类号 |
G06F9/30;G06F9/38;G06F9/46 |
主分类号 |
G06F9/30 |
代理机构 |
|
代理人 |
Pessetto John R.;Brill Charles A.;Cimino Frank D. |
主权项 |
1. A processor, comprising:
a plurality of execution units, at least one of the execution units is configured to:determine, based on a field of a first instruction, a number of additional instructions to execute prior to completion of execution of the first instruction;
wherein the at least one execution unit is configured to determine, based on the field of the first instruction, a number of additional instructions to execute without interruption with the first instruction; wherein other execution units in the plurality of execution units execute the additional instruction; wherein the field of the first instruction specifies at least one of: a first number of additional instructions to be executed without interruption with the first instruction; a second number of additional instructions to be executed with the first instruction wherein the second number of additional instructions maybe interrupted; a third number of additional instructions that are to be executed subsequent to execution of the first number of additional instructions wherein the third number of additional instructions maybe interrupted; and a fourth number of additional instructions that are to be executed without interruption subsequent to the execution of the second number of additional instructions. |
地址 |
Freising DE |