发明名称 Image processing apparatus
摘要 A frame image signal which is output cyclically is converted to a digital signal and input to a first multiplier in a digital filter. The first multiplier multiplies a digital image signal Yi of each frame by (1-a), and supplies the product (1-a)xYi to a first input terminal of an adder. The coefficient a is a negative coefficient whose absolute value is not more than 1, so that (1-a) becomes a positive coefficient of not less than 1. An output of the adder serves as an output Yi' of the digital filter from which the residual image has been erased, and is supplied to a subsequent unit, e.g., a display unit (not shown) connected to the output of the adder. The output Yi' of the adder is also supplied to a frame memory and is delayed by one frame period. Therefore, an output Yi-1' of the frame memory is a one-frame preceding image output. The signal Yi-1' is input to a second multiplier and is multiplied by the coefficient a. The product is input to a second input terminal of the adder.
申请公布号 US5392211(A) 申请公布日期 1995.02.21
申请号 US19910799281 申请日期 1991.11.27
申请人 KABUSHIKI KAISHA TOSHIBA 发明人 OE, MITSUO
分类号 G01N21/88;A61B6/00;A61B6/02;G06T5/20;H04N5/21;H04N5/243;H04N5/32;H04N7/18;(IPC1-7):G06F15/42 主分类号 G01N21/88
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