| 摘要 |
PROBLEM TO BE SOLVED: To provide a circuit which can be applied to data transmission at high speed by detecting a timing of collating a synchronizing pattern by detection at the time of change from a second logical level to a first logical level. SOLUTION: When serial data is not transmitted from a data signal line, a logical level is fixed to the first logical level to fix the second logical level to the leading bit of a synchronizing pattern and to fix the first logical data to the next bit. In this circuit, a collation part 8 collates the three-bit pattern of a part suitable for detecting a synchronizing pattern among 20 bits latched by a received data shift register 5 with a synchronizing pattern 010 stored in a synchronizing pattern storing part 7 with a timing detected by a count value from a counter 9, and when they are matched with each other, a coincidence signal is given to a clock frequency dividing circuit 10. |
