| 摘要 |
PROBLEM TO BE SOLVED: To provide an input buffer circuit for semiconductor integrated circuit in which a test pattern having a high failure detection rate can be realized in the IDDQ test while interrupting leak current. SOLUTION: When a test enable signal TIB is 'L' level, an 'H' level signal is inputted to the enable terminal IT of a differential circuit 2 which functions as a normal differential circuit. Terminal B of an input switching circuit 3 is selected and the output signal Q from the differential circuit 2 is delivered as an output signal OUT. In the IDDQ test, the test enable signal TIB is brought to 'H≈level. Consequently, the enable terminal IT of the differential circuit 2 is brought to 'L' level, and through current thereof is interrupted. Terminal A of the input switching circuit 3 is thereby selected and the input signal IN is delivered as an output signal OUT.
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