| 摘要 |
In a microprocessor, a speculative acknowledge/rescue scheme is implemented in the bus controller to increase bus cycle performance for +E,fra 1/2+EE X clocking. For the odd cycles of the bus controller clock that result from +E,fra 1/2+EE X clocking, bus cycle requests from the cache controller, which ordinarily cannot be acknowledged in the same bus controller clock as received (even though the bus cycle can still be run the that clock), are speculatively acknowledged. If the bus controller cannot run the bus cycle in that clock, rescue is initiated in which the bus cycle request is resubmitted in the next clock. In an exemplary embodiment, snoop write back requests are prioritized such that a pending rescue bus cycle will be stalled until the snoop write back request is completed. The speculative acknowledge/rescue scheme is advantageous in minimizing any adverse impact on performance by minimizing the number of unacknowledged bus cycle requests during odd clock cycles created by +E,fra 1/2+EE X clocking.
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