High speed integrated circuit interface

摘要

A method and apparatus for interfacing integrated circuit chips is disclosed. In one embodiment, the interface includes a set of differential data lines over which a variable length register transaction can be conducted.

主权项

1. An integrated circuit chip, comprising:
a logic core operable to control a second integrated circuit chip; a differential clock output for providing a timing reference signal to the second integrated circuit chip; a set of differential data outputs for transmitting an address over a set of differential data lines to the second integrated circuit chip; and an output to transmit a signal indicating a length of a variable length register transaction based on a time period the signal is asserted, wherein the length of the register transaction is different from the length of a previous register transaction between the integrated circuit chip and the second integrated circuit chip.