| 发明名称 |
HIGH PERFORMANCE INTERCONNECT LINK STATE TRANSITIONS |
| 摘要 |
A supersequence is sent to another device to indicate a transition from a partial width link state to another active link state. The supersequence is to be sent over one or more lanes of a link and is to include at least a portion of a start of data sequence (SDS) to include a predefined sequence and a byte number value. The byte number value is to indicate a number of bytes measured from a preceding control interval. |
| 申请公布号 |
US2016179730(A1) |
申请公布日期 |
2016.06.23 |
| 申请号 |
US201414578175 |
申请日期 |
2014.12.19 |
| 申请人 |
Intel Corporation |
发明人 |
Halleck William R.;Shah Rahul;Iyer Venkatraman |
| 分类号 |
G06F13/40;G06F13/42 |
主分类号 |
G06F13/40 |
| 代理机构 |
|
代理人 |
|
| 主权项 |
1. An apparatus comprising:
protocol logic to send a supersequence to another device to indicate a transition from a partial width link state to another active link state, wherein the supersequence is to be sent over one or more lanes of a link and is to comprise at least a portion of a start of data sequence (SDS) to comprise a predefined sequence and a byte number value, and the byte number value is to indicate a number of bytes measured from a preceding control interval. |
| 地址 |
Santa Clara CA US |
