ADDRESS TRANSLATION CACHE THAT SUPPORTS SIMULTANEOUS INVALIDATION OF COMMON CONTEXT ENTRIES

摘要

A processor includes a mapping module that maps architectural virtual processor identifiers to non-architectural global identifiers and maps architectural process context identifiers to non-architectural local identifiers. The processor also includes a translation-lookaside buffer (TLB) having a plurality of address translations. For each address translation of the plurality of address translations: when the address translation is a global address translation, the address translation is tagged with a representation of one of the non-architectural global identifiers to which the mapping module has mapped one of the virtual processor identifiers; and when the address translation is a local address translation, the address translation is tagged with a representation of one of the non-architectural local identifiers to which the mapping module has mapped one of the process context identifiers.

主权项

1. A translation-lookaside buffer (TLB), comprising:
a plurality of entries, wherein each entry of the plurality of entries is configured to hold an address translation and a valid bit vector, wherein each bit of the valid bit vector indicates, for a respective address translation context, the address translation is valid if set and invalid if clear; and an invalidation bit vector having bits corresponding to the bits of the valid bit vector of the plurality of entries, wherein a set bit of the invalidation bit vector indicates to simultaneously clear the corresponding bit of the valid bit vector of each entry of the plurality of entries.