发明名称 MULTI-CORE PROGRAMMING APPARATUS AND METHOD FOR RESTORING DATA ARRAYS FOLLOWING A POWER GATING EVENT
摘要 An apparatus includes a programmer, a stores, and a plurality of cores. The programmer programs a fuse array with compressed configuration data. The stores provides for storage and access of decompressed configuration data sets. Each of a plurality of cores is coupled to the fuse array. One of the cores is accesses the fuse array upon power-up/reset to decompress and store decompressed configuration data sets for one or more cache memories. Each of the cores includes reset logic and sleep logic. The reset logic employs the decompressed configuration data sets to initialize the one or more cache memories upon power-up/reset. The sleep logic determines that power is restored following a power gating event, and subsequently accesses the stores to retrieve and employ the decompressed configuration data sets to initialize the one or more caches following the power gating event.
申请公布号 US2016179692(A1) 申请公布日期 2016.06.23
申请号 US201414889846 申请日期 2014.12.12
申请人 VIA ALLIANCE SEMICONDUCTOR CO., LTD. 发明人 HENRY G. GLENN;JAIN DINESH K.;GASKINS STEPHAN
分类号 G06F12/08 主分类号 G06F12/08
代理机构 代理人
主权项 1. An apparatus for providing configuration data to an integrated circuit, the apparatus comprising: a device programmer, coupled to a semiconductor fuse array disposed on a die, configured to program said semiconductor fuse array with compressed configuration data; a stores, also disposed on said die, configured for storage and access of decompressed configuration data sets; and a plurality of cores, also disposed on said die, wherein each of said plurality of cores is coupled to said semiconductor fuse array, and wherein one of said plurality of cores is configured to access said semiconductor fuse array upon power-up/reset to read and decompress said compressed configuration data, and to store said decompressed configuration data sets for one or more cache memories within said each of said plurality of cores in said stores, said each of said plurality of cores comprising: reset logic, configured to employ said decompressed configuration data sets to initialize said one or more cache memories upon power-up/reset; andsleep logic, configured to determine that power is restored following a power gating event, and configured to subsequently access said stores to retrieve and employ said decompressed configuration data sets to initialize said one or more caches following said power gating event.
地址 Shanghai CN