STATELESS CAPTURE OF DATA LINEAR ADDRESSES DURING PRECISE EVENT BASED SAMPLING

摘要

A processor includes a logic for stateless capture of data linear addresses (DLA) during precise event based sampling (PEBS) for an out-of-order execution engine. The engine may include a PEBS unit with logic to increment a counter each time an instance of a designated micro-op is retired a reorder buffer, capture output DLA referenced by an instance of the micro-op that executes after the counter overflows, set a captured bit associated with a reorder buffer identifier for the instance of the micro-op, and store a PEBS record in a debug storage when the instance of the micro-op is retired from the reorder buffer. The designated micro-op references a DLA of a memory accessible to the processor.

主权项

1. A processor, comprising:
a front end including a first logic to decode instructions and issue micro-ops; an out-of-order execution engine including:
an allocation and scheduling unit including a second logic to receive micro-ops from the front end, to allocate resources for the micro-ops, and to enter the micro-ops into a reorder buffer;an execution unit including third logic to access micro-ops from the reorder buffer and execute the micro-ops;the reorder buffer including fourth logic to track execution of micro-ops with reorder buffer identifiers; anda retirement unit including fifth logic to retire micro-ops after execution by the execution unit; and a performance event based sampling (PEBS) unit, including:
a sixth logic to increment a counter each time an instance of a designated micro-op in an out-of-order engine is retired from the reorder buffer, wherein the designated micro-op references a data linear address (DLA) of a memory accessible to the processor;a seventh logic to capture, in a DLA register, a first output DLA referenced by a first instance of the micro-op that executes after the counter overflows;an eighth logic to set a captured bit associated with a reorder buffer identifier for the first instance of the micro-op; anda ninth logic to store a PEBS record in a debug storage when the first instance of the micro-op is retired from the reorder buffer, wherein the PEBS record is to include the first output DLA from the DLA register.