COMPILER METHOD FOR GENERATING INSTRUCTIONS FOR VECTOR OPERATIONS ON A MULTI-ENDIAN PROCESSOR

摘要

A compiler includes a vector instruction processing mechanism that generates instructions for vector instructions in a way that assures correct operation in a bi-endian environment, wherein the processor architecture contains instructions with an inherent endian bias. The compiler uses a code generation endian preference that is specified by the user, and that determines a natural element order. When the compiler processes a computer program, it generates instructions for vector operations by determining whether the vector instruction has an endian bias that matches the specified endian preference. When the vector instruction has no endian bias, or when the endian bias of the vector instruction matches the specified endian preference, the compiler generates one or more instructions for the vector instruction as it normally does. When the endian bias of the vector instruction does not match the specified endian preference, the compiler generates instructions to fix the mismatch.

主权项

1. An apparatus comprising:
at least one processor; a memory coupled to the at least one processor; a computer program residing in the memory, the computer program including a plurality of instructions; an endian preference for the apparatus that defines a natural element order for vector instructions; and a compiler residing in the memory and executed by the at least one processor, the compiler including a vector instruction processing mechanism that determines when a vector instruction has an inherent element order that is a mismatch to the natural element order, and in response, generates at least one instruction to fix the mismatch.