Package including a plurality of stacked semiconductor devices including a capacitance enhanced through via and method of manufacture

摘要

A plurality of semiconductor memory devices on a multi-chip package is disclosed. Each semiconductor device may include a plurality of through vias and a plurality of capacitance enhanced through vias. The through vias may provide an electrical connection for signals that may transition between logic states. The capacitance enhanced through vias may provide an electrical connection from a first side to a second side of the respective semiconductor device for transmission signals that remain substantially stable such as reference voltages, power supply voltages or the like. In this way, noise may be reduced and a reservoir of charge for circuits that provide a load for reference voltages and/or power supply voltages may be provided.

主权项

1. A package, comprising:
a first semiconductor device, a second semiconductor device, and a third semiconductor device stacked in a first direction; the first semiconductor device including
a first through via providing a first electrical connection in the first direction between a first side and a second side opposite the first side of the first semiconductor device; anda first circuit, the first circuit provides a first reference potential at a first circuit output, the first circuit output is electrically connected to the first through via at the first side when the first semiconductor device is in a normal mode of operation; and the second semiconductor device including
a second through via providing a second electrical connection in the first direction between a first side and a second side opposite the first side of the second semiconductor device wherein the second semiconductor device includes a second circuit having a second circuit output electrically connected to the first through via at the second side of the first semiconductor device and the third semiconductor device is electrically connected to the second through via at the second side of the second semiconductor device to receive the first reference potential, the first circuit and the second circuit provide the first reference potential.