发明名称 |
Nonvolatile semiconductor memory device having row decoder supplying a negative potential to word lines during erase mode |
摘要 |
A nonvolatile semiconductor memory device is provided in which a negative voltage is applied to a gate electrode of a memory cell transistor during an erase mode. The memory device includes a row decoder circuit having an N-channel transistor connected to a word line. The N-channel transistor is provided on a P-type well region of a semiconductor substrate. A negative voltage is applied to the P-type well region during the erase mode, while ground potential is applied thereto during another modes.
|
申请公布号 |
US5392253(A) |
申请公布日期 |
1995.02.21 |
申请号 |
US19920918027 |
申请日期 |
1992.07.24 |
申请人 |
KABUSHIKI KAISHA TOSHIBA |
发明人 |
ATSUMI, SHIGERU;TANAKA, SUMIO |
分类号 |
G11C17/00;G11C7/00;G11C8/00;G11C8/08;G11C16/06;G11C16/08;G11C16/14;H01L21/8247;H01L27/10;H01L27/115;(IPC1-7):G11C8/00 |
主分类号 |
G11C17/00 |
代理机构 |
|
代理人 |
|
主权项 |
|
地址 |
|