ANALYSIS METHOD OF LINEAR CIRCUIT NETWORK FOR ANALYZING VOLTAGE DROP IN SEMICONDUCTOR INTEGRATED CIRCUIT AT HIGH SPEED

摘要

PURPOSE: An analysis method of a linear circuit network for analyzing a voltage drop in a semiconductor integrated circuit at high speed is provided to shorten the time to analyze the linear circuit network of the semiconductor integrated circuit. CONSTITUTION: A resistance value of a power line and power consumption values of every instance in a layout of a semiconductor integrated circuit are inputted. An equivalent resistance circuit network is obtained from the layout based upon the resistance value of the power line. The power consumption of every instance in the equivalent resistance circuit network is transformed into an equivalent conductance. When a resistor circuit network wherein both end points of a power rail encounters a core ring or power trunk is defined as a unit placement rho, each unit placement rho of the equivalent resistance circuit network is formed as each equivalent circuit by applying a superposition theorem. Each node voltage inside each unit placement rho formed as each equivalent circuit is calculated regarding every unit placement rho.