| 摘要 |
PROBLEM TO BE SOLVED: To realize fail-safe by also preserving unimportant data in a non- volatile memory every prescribed time without applying load to a CPU. SOLUTION: Power supply voltage +B<αor not is decided, a +B drop counter cbdwn counts up in the case of +B<αand a short break time SRAM processing execution flag is turned on in the case of cbdwn>γ. Also when a short break of power source is generated, the flag is turned on. In the SRAM processing, speed and speed gear stages stored in a control RAM 9b are stored as last trip values after power supply recovery in an SRAM 9c. When the short break time SRAM processing execution flag is on, data except the speed and speed gear stages stored in the control RAM 9b (shift range states, for instance) is stored as the last trip values after power source recovery in the SRAM 9c. When the short break time SRAM processing execution flag is off, data except the speed and speed gear stages is not stored and the SRAM processing is terminated.
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