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发明名称
具漏电流截止电路之半导体积体电路
摘要
在所披露之半导体积体电路中,逻辑电路区块之多数个电源供应端点经由漏电流截止电路被连接到实际电源供应线。当逻辑电路区块将被引动时,延迟控制电路则控制漏电流截止电路以便以预定时间延迟而电气连接电源供应端点至实际电源供应线。因此,当逻辑电路区块被引动时,实际电源供应线之电压降可以被降低至微小值,并且由于电源供应杂讯所造成之在被致动状况之逻辑电路区块的错误操作亦可以被防止。
申请公布号
TW200306707
申请公布日期
2003.11.16
申请号
TW092106088
申请日期
2003.03.19
申请人
富士通股份有限公司
发明人
宫城觉
分类号
H03K19/0948
主分类号
H03K19/0948
代理机构
代理人
恽轶群;陈文郎
主权项
地址
日本
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