Critical region identification

摘要

A method and system to identify a region of a design block of an integrated circuit for redesign are described. The method includes dividing the design block into grids, each of the grids including a corresponding number of logic elements. The method also includes filtering each of the grids based on a specified criteria, the filtering including determining a number (B) of the corresponding logic elements among a total number (A) of the logic elements in each grid that meet the specified criteria. The region is a set of two or more of the grids based on a result of the filtering.

主权项

1. A processing system to identify a region of a design block of an integrated circuit for redesign, the system comprising:
a processor configured to divide the design block into grids, each of the grids including a respective number of logic elements, filter each of the grids based on a specified criticality criteria, the filtering including determining a total number (A) of the logic elements in each grid and a number (B) of the total number (A) of the logic elements in each grid that meet the specified criticality criteria, compute a power efficiency score (PES) for each of the total number (A) of the logic elements in each grid as:PES=CDS_assignment⁢_score×VT_assignment⁢_scoreslack_achievement⁢_score×slew_achievement⁢_score,where
CDS_assignment_score being based on a minimum and maximum cell drive strength (CDS) for each of the logic elements of each of the grids, VT_assignment_score being based on a threshold voltage (VT) used for the logic element, slack_achievement_score being based on slack as compared with a target slack, and slew_achievement_score being based on slew as compared with a target slew, and identify the region as a set of two or more of the grids based on a result of the filtering; and a display device configured to display the result of the filtering.