Active matrix light emitting diode array and projector display comprising it

摘要

A method of fabricating a pixelated projector display includes providing a wafer with a supporting substrate, a first semiconductive layer, an emission layer, and a second semiconductive layer. The wafer is patterned into an array of LEDs/LDs and a planarization layer is deposited over the array. One via for each LED/LD element is formed through the planarization layer. A MOTFT backplane is positioned on the planarization layer, one driver circuit in controlling electrical communication with each via through the planarization layer. A passivation layer is deposited over the MOTFT backplane and heat plugs are extended through the passivation layer, the MOTFT backplane, the planarization layer, and the III-V LED/LD wafer partially through the first semiconductive layer to thermally couple heat from the array of LEDs/LDs to the surface of the passivation layer. An upper end of the heat plugs is accessible for thermal coupling to a heat spreader and/or a heatsink.

主权项

1. A method of fabricating a pixelated projector display comprising the steps of:
providing a III-V LED/LD wafer including a supporting substrate, a first type semiconductive layer on the substrate, and a second or opposite type semiconductive layer overlying the first type semiconductor layer; patterning the III-V LED/LD wafer into an array of LEDs/LDs; depositing a planarization layer over the array of LEDs and forming vias through the planarization layer, one via for each LED/LD in the LED/LD array; forming a MOTFT backplane including an array of MOTFT pixel driver circuits on the planarization layer, one driver circuit in controlling electrical communication with each via through the planarization layer, whereby an AMLED/AMLD display is formed; depositing a passivation layer over the array of MOTFT driver circuits; and extending heat plugs between adjacent LEDs/LDs in the LED/LD array through the passivation layer, the MOTFT backplane, the planarization layer, and the III-V LED/LD wafer partially through the first type semiconductive layer to thermally couple heat from the array of LEDs/LDs to the surface of the passivation layer, an upper end of the heat plugs being accessible for thermally coupling to a heat spreader and/or a heatsink.