发明名称 |
Page or word-erasable composite non-volatile memory |
摘要 |
A non-volatile memory includes bit lines, a first page-erasable sector including memory cells of a first type, and a second word-erasable or bit-erasable sector including memory cells of a second type. The memory cells of the first type comprise a single floating-gate transistor and the memory cells of the second type comprise a first floating-gate transistor and a second floating-gate transistor the floating gates of which are electrically coupled, the second floating-gate transistor of a memory cell of the second type enabling the memory cell to be individually erased. |
申请公布号 |
US9460798(B2) |
申请公布日期 |
2016.10.04 |
申请号 |
US201514795742 |
申请日期 |
2015.07.09 |
申请人 |
STMicroelectronics (Rousset) SAS |
发明人 |
La Rosa Francesco |
分类号 |
G11C16/04;G11C16/14;H01L29/66;H01L29/788;H01L27/115;G11C16/08;G11C16/26 |
主分类号 |
G11C16/04 |
代理机构 |
Seed IP Law Group PLLC |
代理人 |
Seed IP Law Group PLLC |
主权项 |
1. A non-volatile memory on a semiconductor substrate, comprising:
bit lines, first memory cells of a first type each including a single floating-gate transistor, the floating-gate transistor of each of the first memory cells including a drain region electrically coupled to a first bit line of the bit lines, second memory cells of the first type each including a single floating-gate transistor, the floating-gate transistor of each of the second memory cells including a drain region electrically coupled to a second bit line of the bit lines, and memory cells of a second type each including:
a first floating-gate transistor including a floating gate and a drain region electrically coupled to the first bit line, anda second floating-gate transistor including a floating gate and a drain region electrically coupled to the second bit line, wherein the floating gate of the first floating-gate transistor is electrically coupled to the floating gate of the second floating-gate transistor, and the second floating-gate transistor comprises a tunnel dielectric layer and a permanently conductive region extending on an opposite side of the tunnel dielectric layer with respect to the floating gate of the second floating-gate transistor. |
地址 |
Rousset FR |