System and method for detecting loss of signal

摘要

Apparatus and methods are taught for quickly determining whether a Loss of Signal (LOS) condition has occurred for a receiver which includes an internal reference clock, a LOS circuit and a Clock and Data Recovery (CDR) circuit. The CDR circuit recovers the clock and data of an incoming signal. However, the LOS circuit can determine whether a received incoming signal includes an active signal, independent of said CDR circuit such that it samples said incoming signal utilizing said internal reference clock to determine a loss of signal prior to said CDR recovering the clock of said incoming signal. The LOS circuit includes an analog voltage threshold stage which samples the incoming signal, and produces at least one sample stream indicative of transitions in the incoming signal. The LOS circuit further includes a digital transition stage which counts transitions in order to discriminate between an active signal and noise.

主权项

1. A receiver comprising:
a signal receive interface for receiving an incoming signal; an internal reference clock source for producing an internal reference clock signal, said internal reference clock signal being asynchronous to a clock rate of said incoming signal; and a loss of signal (LOS) circuit which samples said incoming signal utilizing said internal reference clock signal to determine whether a loss of signal condition has occurred; said LOS circuit comprising: an analog threshold stage which samples said incoming signal, and produces at least one sample stream indicative of transitions in said incoming signal; and a digital transition stage which counts transitions in said at least one sample stream in order to discriminate between an active signal and a loss of signal condition wherein a transition occurs when a signal value of said incoming signal crosses a first reference threshold and a second reference threshold; and wherein said analog threshold stage comprises: a level comparator for comparing said input signal with said first and second reference thresholds; a first circuitry coupled to the output of said comparator and said internal reference clock signal for sampling the output from the comparator; and a second circuitry coupled to the output of said comparator and a phase shifted version of the internal reference clock signal for sampling the output from said comparator.