Separating bits represented by a MLC in connection with ECC

摘要

Two-terminal memory can be configured as multi-level cell (MLC) memory in which a single memory cell can represent multiple bits of information. Unlike certain other memories that are subject to disturb errors, for the disclosed two-terminal memory, these multiple bits can store information that is included in the same logical page of memory, which can be advantageous. However, performing error-code correction (ECC) operations on multiple bits of data from the same MLC can result in additional stress on an ECC engine because if a MLC fails, all bits of that cell are likely to be bad. Splitting the multiple bits of a MLC in connection with encoding or decoding can average the errors from bad cells across multiple ECC codewords, thereby providing better coverage with the same ECC or reducing the overhead associated with ECC coverage.

主权项

1. A memory device, comprising:
a controller device that interfaces to a host device and to an array of memory cells, wherein each memory cell comprises a multi-level cell (MLC), wherein the MLC is characterized by a plurality of measurable states represented by multiple bits of data; a splitter component that generates split data characterized by assigning a first bit of the multiple bits of data to a first codeword of a page of memory and a second bit of the multiple bits of data to a second codeword of the page of memory; and an error-correcting code (ECC) component that detects and corrects bit errors associated with the multiple bits of data in response to the first codeword, the second codeword and an ECC algorithm.